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a ad1980 ac ?7 soundmax ? codec rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2002 analog devices, inc. all rights reserved. features ac ?7 2.3 compatible features 6 dac channels for 5.1 surround s/pdif output integrated stereo headphone amplifier variable rate audio double rate audio (f s = 96 khz) greater than 90 db dynamic range 20-bit pcm dacs line-level mono ?hone?input high quality cd input selectable mic input with preamp aux and line_in stereo inputs external amplifier power-down control power management modes 48-lead lqfp package functional block diagram mc1 mc2 phone_in cd_l cd_gnd cd_r aux_l aux_r line_in_l ms g g 2cmic mic preamp cd diff amp m ga m ga m ga m m m ga m ga m ga m ga m ga m m m m g = gain a = attenuation m = mute z = high z m g 16-bit - adc m g 16-bit - adc pcm l/r adc rate record selector v ref g v refout line_in_r codec core vo ltag e reference dac slot logic ac ' 97 interface eq coef storage ac '97 control registers eapd analog mixing control logic pll xtl_out xtl_in spdif spdif tx id0 id1 reset sync bitclk sdata_out sdata_in js0 js1 eapd ad1980 20-bit - dac pcm lfe dac rate m g sprd mz a lfe_out sprd mz a center_out 20-bit - dac pcm front dac rate m g m g m g 20-bit - dac m g 20-bit - dac m g pcm surr dac rate bypass eq 20-bit - dac bypass eq 20-bit - dac mz a line_out_l mz a mono_out mz a line_out_r m a surr_out_l/ hp_out_l m a surr_out_r/ hp_out_r hp hp losel losel hpsel hpsel enhanced features integrated parametric equalizer stereo mic preamp support integrated pll for system clocking variable sample rate 7 khz to 96 khz jack sense (auto topology switching) software controlled vref_out for mic bias software enabled outputs for jack sharing auto down-mix and channel spreading modes
rev. 0 ? ad1980?pecifications parameter min typ max unit analog input input voltage (rms values assume sine wave input) line_in, cd, aux, phone_in 1 v rms 2.83 v p-p mic_in with 30 db preamp 0.032 v rms 0.089 v p-p mic_in with 20 db preamp 0.1 v rms 0.283 v p-p mic_in with 10 db preamp 0.316 v rms 0.894 v p-p mic_in with 0 db gain 1 v rms 2.83 v p-p input impedance * 20 k ? input capacitance * 5 7.5 pf master volume step size (line out, mono out, surround out, center, lfe) 1.5 db output attenuation range span * 46.5 db mute attenuation of 0 db fundamental * 80 db programmable gain amplifier?dc step size (0 db to 22.5 db) 1.5 db pga gain range span 22.5 db analog mixer?nput gain/amplifiers/attenuators signal-to-noise ratio (snr) cd to line_out 90 db line, aux, phone, to line_out * 90 db mic1 or mic2 (note: mic gain of 0 db) to line_out * 90 db step size all mixer inputs 1.5 db input gain/attenuation range: all mixer inputs 46.5 db digital decimation and interpolation filters * pass band 0 0.4 f s hz pass-band ripple 0.09 db transition band 0.4 f s 0.6 f s hz stop band 0.6 f s hz stop-band rejection ?4 db group delay 16/f s sec group delay variation over pass band 0 s standard test conditions, unless otherwise noted temperature 25 c digital supply (dv dd ) 3.3 v analog supply (av dd ) 5.0 v sample rate (f s ) 48 khz input signal 1008 hz analog output pass band 20 hz to 20 khz dac test conditions calibrated ? db attenuation relative to full scale 0 db input 10 k ? output load line_out, mono_out, center_out, and lfe_out 32 ? output load (hp_out) adc test conditions calibrated 0 db gain input ?.0 db relative to full scale
rev. 0 ad1980 ? parameter min typ max unit analog-to-digital converters resolution 16 bits total harmonic distortion (thd) av dd = 5.0 v ?8 db dynamic range (?0 db input thd + n referenced to fs, a-weighted) 82 db av dd = 5.0 v signal-to-intermodulation distortion * (ccif method) 84 db adc crosstalk * line inputs (input l, ground r, read r; input r, ground l, read l) ?5 ?0 db line_in to other ?0 ?5 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.5 db adc offset error * (0 db gain, hpf on) 10 mv digital-to-analog converters resolution 20 bits total harmonic distortion (thd), line_out, av dd = 5.0 v ?0 db total harmonic distortion (thd), hp_out, av dd = 5.0 v ?3 db total harmonic distortion (thd), center/lfe, av dd = 5.0 v ?2.5 db dynamic range (?0 db input thd + n referenced to fs a-weighted) 90 db av dd = 5.0 v signal-to-intermodulation distortion * (ccif method) 88 db gain error (full-scale span relative to nominal input voltage) 10 % interchannel gain mismatch (difference of gain errors) 0.7 db dac crosstalk (input l, zero r, read line_out_r; input r, ?0 db zero l, read line_out_l, 10 k ? load) * total audible out-of-band energy * (measured from 0.6 f s to 20 khz) ?0 db analog output full-scale output voltage; line_out/mono_out, center_out, lfe_out 1v rms 2.83 v p-p output impedance * 800 ? external load impedance * (line_out, center_out/lfe_out, mono_out) 10 k ? output capacitance * 15 pf external load capacitance * 100 pf full-scale output voltage; hp_out (0 db gain) 1 v rms external load impedance * ; hp_out 32 ? v ref 2.05 2.25 2.45 v v ref_out (v refh = 0) 2.25 v v ref_out (v refh = 1) 3.65 v v ref_out current drive 5ma mute click (muted output minus unmuted midscale dac output) 5mv static digital specifications high level input voltage (v ih ): digital inputs 0.65 dv dd v low level input voltage (v il ) 0.35 dv dd v high level output voltage (v oh ), i oh = 2 ma 0.9 dv dd v low level output voltage (v ol ), i ol = 2 ma 0.1 dv dd v input leakage current ?0 +10 a output leakage current ?0 +10 a power supply power supply range; analog (av dd )4.75 5.25 v power supply range; digital (dv dd )3.15 3.45 v power dissipation 5 v/3.3 v 563 mw analog supply current 5 v (av dd )70ma digital supply current 3.3 v (dv dd )53ma power supply rejection (100 mv p-p signal @ 1 khz) * 40 db (at both analog and digital supply pins, both adcs and dacs) * guaranteed but not tested. specifications subject to change without notice.
rev. 0 ? ad1980 parameter pr[k:i] 1 pr[6:0] 1 dv dd typ av dd typ unit power-down states 2 fully active 000 000 0000 53 70 ma adc 000 000 0001 44 66 ma front dac 000 000 0010 46 61 ma surround dac 010 000 0000 46 61 ma center/lfe dac 101 000 0000 46 61 ma adc + all dacs 111 000 0011 12 33 ma mixer 000 000 0100 52 44 ma adc + mixer 000 000 0101 45 39 ma all dacs + mixer 111 000 0110 31 14 ma adc + all dacs + mixer 111 000 0111 12 8 ma standby 111 011 1111 0 0 ma headphone standby 000 100 0000 52 65 ma notes 1 pr bits are controlled in reg. 2ah and 26h 2 values presented with v refout loaded. specifications subject to change without notice. parameter symbol min typ max unit reset active low pulsewidth t rst_low 1.0 s reset inactive to bit_clk startup delay t rst2clk 162.8 400,000 ns sync active high pulsewidth t sync_high 1.3 s sync low pulsewidth t sync_low 19.5 s sync inactive to bit_clk startup delay t sync2clk 162.8 ns bit_clk frequency 12.288 mhz bit_clk frequency accuracy 1.0 ppm bit_clk period t clk_period 81.4 ns bit_clk output jitter 1, 2 750 ps bit_clk high pulsewidth t clk_high 40 41.7 ns bit_clk low pulsewidth t clk_low 39.7 41.4 ns sync frequency 48.0 khz sync period t sync_period 20.8 s setup to falling edge of bit_clk t setup 4ns hold from falling edge of bit_clk t hold 3ns bit_clk rise time t riseclk 246ns bit_clk fall time t fallclk 246ns sync rise time t risesync 246ns sync fall time t fallsync 246ns sdata_in rise time t risedin 246ns sdata_in fall time t falldin 246ns sdata_out rise time t risedout 246ns sdata_out fall time t falldout 246ns end of slot 2 to bit_clk, sdata_in low t s2_pdown 0 1.0 s setup to reset inactive (sync, sdata_out) t setup2rst 15 ns rising edge of reset to hi-z delay t off 25 ns propagation delay 15 ns reset rise time 50 ns output valid delay from bit_clk rising 15 ns notes 1 guaranteed but not tested. 2 output jitter directly dependent on crystal input jitter. specifications subject to change without notice. timing parameters (guaranteed over operating temperature range) parameter min typ max unit clock specifications * input clock frequency (xtal mode or clock oscillator) 24.576 mhz input clock frequency (reference clock mode) 14.31818 mhz input clock frequency (usb clock mode) 48.000 mhz recommended clock duty cycle 40 50 60 % * guaranteed but not tested. specifications subject to change without notice.
rev. 0 ad1980 ? reset bit_clk sdata_in t rst_low t rst2clk t tri2actv t tri2actv figure 1. cold reset timing (codec is supplying the bit_clk signal) sync bit_clk t sync_high t sync2clk figure 2. warm reset timing bit_clk sync t clk_low t clk_high t clk_period t sync_low t sync_period t sync_high figure 3. clock timing bit_clk sync sdata_in sdata_out t riseclk t fallclk t risesync t fallsync t risedin t falldin t risedout t falldout figure 4. signal rise and fall times bit_clk sync sdata_in sdata_out bit_clk not to scale slot 1 slot 2 write to 0 26 data pr4 t s2_pdown figure 5. ac-link low power mode timing bit_cl sdata_o sdata_i syn t co t setup v ih v il v oh v ol t hold figure 6. ac-link low power mode timing reset sdata_out sdata_in, bit_clk, eapd, spdif_out and digital i/o hi-z t setup2rst t off figure 7. ate test mode
rev. 0 ? ad1980 absolute maximum ratings * parameter min max unit power supplies digital (dv dd ) ?.3 +3.6 v analog (av dd ) ?.3 +6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) ?.3 av dd + 0.3 v digital input voltage (signal pins) ?.3 dv dd + 0.3 v ambient temperature (operating) 0 70 c storage temperature ?5 +150 c * stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration 48-lead lqfp 1 2 3 4 5 6 7 8 9 10 11 12 dv dd 1 xtl_in xtl_out dv ss 1 sdata_out bit_clk dv ss 2 sdata_in dv dd 2 sync reset nc 36 35 34 33 32 31 30 29 28 27 26 25 line_out_r (front_r) line_out_l (front_l) av dd 4 av ss 4 lfe_out center_out afilt2 afilt1 v refout v ref av ss 1 av dd 1 13 14 15 16 17 18 19 20 21 22 23 24 phone_in aux_l aux_r js1 js0 cd_l cd_gnd_ref cd_r mc1 mc2 line_in_l line_in_r 48 47 46 45 44 43 42 41 40 39 38 37 spdif eapd id1 id0 av ss 3 av dd 3 nc surr_out_r/hp_out_r av ss 2 surr_out_l/hp_out_l av dd 2 mono_out ad1980 top view (not to scale) nc = no connect environmental conditions * ambient temperature rating tcase = case temperature in c pd = power dissipation in w ja = thermal resistance (junction-to-ambient) jc = thermal resistance (junction-to-case) ordering guide model temperature range package description package option * ad1980jst 0 c to 70 c 48-lead lqfp st-48 * st = low profile quad flatpack package ja jc lqfp 50.1 c/w 17.8 c/w * all measurements per eia/jesd51 with 2s2p test board per eia/jesd51-7. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1980 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. 0 ad1980 ? pin function descriptions pin number mnemonic i/o function digital input/output 2 xtl_in i crystal input (24.576 mhz) or external clock in (24.576 mhz, 14.31818 mhz or 48000 mhz) 3 xtl_out o crystal output 5 sdata_out i ac-link serial data output. ad1980 input stream. 6b it_ clk o/i ac-link bit clock. 12.288 mhz serial data clock. (input pin, for secondary mode only.) 8 sdata_in o ac-link serial data input. ad1980 output stream. 10 sync i ac-link frame sync 11 reset i ac-link reset. ad1980 master h/w reset. 48 spdif o spdif output chip selects/clock strapping 45 id0 ic hip select input 0 (active low). this pin can also be used as the chain input from a secondary codec. 46 id1 ic hip select input 1 (active low) jack sense and eapd 47 eapd o eapd output 17 js0 i jack sense 0 input 16 js1 i jack sense 1 input analog input/output 13 phone_in i monaural line-level input 14 aux_l i auxiliary input, left channel 15 aux_r i auxiliary input, right channel 18 cd_l i cd audio left channel 19 cd_gnd_ref i cd audio analog ground reference for differential cd input 20 cd_ r i cd audio right channel 21 mic1 i microphone #1 input (left channel when 2-channel mode selected) 22 mic2 i microphone #2 input (right channel when 2-channel mode selected) 23 line_in_l i line-in left channel 24 line_in_r i line-in right channel 31 center_out o center channel output 32 lfe_out o low frequency enhanced output 35 line_out_l o line-out (front) left channel 36 line_out_r o line-out (front) right channel 37 mono_out o monaural output to telephone subsystem speakerphone 39 surr_out_l/hp_out_l o surround or front h eadphone left channel output 41 surr_out_r/hp_out_r o surround or front headphone right channel output filter/reference 27 v ref ov oltage reference filter 28 v refout ov oltage reference output 5 ma drive (intended for mic bias) 29 afilt1 o antialiasing filter capacitor?dc right channel 30 afilt2 o antialiasing filter capacitor?dc left channel
rev. 0 ? ad1980 pin number mnemonic i/o function power and ground signals 1dv dd 1i digital v dd 3.3 v 4dv ss 1i digital gnd 7dv ss 2i digital gnd 9dv dd 2i digital v dd 3.3 v 25 av dd 1i analog v dd 5.0 v 26 av ss 1i analog gnd 33 av ss 4i analog gnd 34 av dd 4i analog v dd 5.0 v 38 av dd 2i analog v dd 5.0 v 40 av ss 2i analog gnd 43 av dd 3i analog v dd 5.0 v 44 av ss 3i analog gnd no connects 12 nc no connect 42 nc no connect
rev. 0 ad1980 ? indexed control registers reg name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0090h 02h master volume mm x lmv5 lmv4 lmv3 lmv2 lmv1 lmv0 mmrm * x rmv5 rmv4 rmv3 rmv2 rmv1 rmv0 8000h 04h headphone hpm x lhv5 lhv4 lhv3 lhv2 lhv1 lhv0 hprm * x rhv5 rhv4 rhv3 rhv2 rhv1 rhv0 8000h volume 06h mono volume mvm x x x x x x x x x mv5 mv4 mv2 mv2 mv1 mv0 8000h 0ch phone volume phm x x x x x x x x x x phv4 phv3 phv2 phv1 phv0 8008h 0eh mic volume mcm x x x x x x x x m20 x mcv4 mcv3 mcv2 mcv1 mcv0 8008h 10h line in volume lvm x x llv4 llv3 llv2 llv1 llv0 lvrm * xx rlv4 rlv3 rlv2 rlv1 rlv0 8808h 12h cd volume cvm x x lcv4 lcv3 lcv2 lcv1 lcv0 cdrm * xx rcv4 rcv3 rcv2 rcv1 rcv0 8808h 16h aux volume avm x x lav4 lav3 lav2 lav1 lav0 avrm * xx rav4 rav3 rav2 rav1 rav0 8808h 18h pcm out vol om x x lov4 lov3 lov2 lov1 lov0 omrm * xx rov4 rov3 rov2 rov1 rov0 8808h 1ah record select x x x x x ls2 ls1 ls0 x x xxx rs2 rs1 rs0 0000h 1ch record gain im x x x lim3 lim2 lim1 lim0 imrm x x x rim3 rim2 rim1 rim0 8000h 20h general purpose x x x x drss1 drss0 x ms lpbk x xxxxxx 0000h 24h audio int. i4 x x x i0 x x x x x x x pg3 pg2 pg1 pg0 xxxx and paging 26h power-down eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 0na ctrl/stat 28h ext? audio id id1 id0 x x rev1 rev0 amap ldac sdac cdac dsa1 dsa0 x spdif dra vras x3c7h 2ah ext? audio vforce x prk prj pri spcv x eldac esdac ecdac spsa1 spsa0 x espdif edra evra 0xx0h stat/ctrl 2ch pcm front srf15 srf14 srf13 srf12 srf11 srf10 srf9 srf8 srf7 srf6 srf5 srf4 srf3 srf2 srf1 srf0 bb80h dac rate 2eh pcm surr srs15 srs14 srs13 srs12 srs11 srs10 srs9 srs8 srs7 srs6 srs5 srs4 srs3 srs2 srs1 srs0 bb80h dac rate 30h pcm c/lfe srcl15 srcl14 srcl13 srcl12 srcl11 srcl10 srcl9 srcl8 srcl7 srcl6 srcl5 srcl4 srcl3 srcl2 srcl1 srcl0 bb80h dac rate 32h pcm sra15 sra14 sra13 sra13 sra11 sra10 sra9 sra8 sra7 sra6 sra5 sra4 sra3 sra2 sra1 sra0 bb80h adc rate 36h center/lfe lm x lfe5 lfe4 lfe3 lfe2 lfe1 lfe0 cm x cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 8080h volume 38h surround volume mute_l x lsr5 lsr4 lsr3 lsr2 lsr1 lsr0 mute_r x rsr5 rsr4 rsr3 rsr2 rsr1 rsr0 8080h 3ah spdif control v x spsr1 spsr0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy /aud pro 2000h 60h eq ctrl eqm x x x x x x x sym chs bca5 bca4 bca3 bca2 bca1 bca0 8080h 62h eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0000h 72h jack sense js1 js1 js0 js js js js1 js0 js1 js0 js1 js0 js1 js0 js1 js0 0000h sprd dmx dmx mt2 mt1 mt0 eqb eqb tmr tmr md md st st int int 74h serial slot 16 regm2 regm1 regm0 regm3 drf x chen x lbk1 lbk0 ints x spal spdz splnk 1001h configuration 76h misc control dacz ac97nc msplt lodis cldis hpsel dmix1 dmix0 sprd 2cmic losel sru vrefh vrefd mbg1 mbg0 0000h bits 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4144h 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5370h notes all registers not shown and bits containing an x are assumed to be reserved. odd register addresses are aliased to the next lower even address. reserved registers should not be written to. zeros should be written to reserved bits. * for ac ?7 compatibility, bit d7 is only available by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect.
rev. 0 ?0 ad1980 master volume register (index 02h) reg no. name d15 d14 d13 1 d12 d11 d10 d9 d8 d7 d6 d5 1 d4 d3 d2 d1 d0 default 02h master mm x lmv5 lmv4 lmv3 lmv2 lmv1 lmv0 mmrm 2 xr mv5 rmv4 rmv3 rmv2 rmv1 rmv0 8000h volume notes 1 refer to table i for examples. this register controls the line_out volume controls for both stereo channels and mute bit. each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 db each. because ac ?7 defines 6-bit volume registers, to maintain compatibil ity whenever the d5 or d13 bits are set to ?,?their respective lower five volume bits are automatically set to ??by the codec logic. on readback, all lower five bits will read ?s?whenever these bits are set to ?. 2 for ac ?7 compatibility, bit d7 is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect. all registers not shown and bits containing an x are assumed to be reserved. note that depending on the state of the ac97nc bit in register 0x76, this register has the following additional functionality: for ac97nc = 0, the register controls the line_out output attenuators only. for ac97nc = 1, the register controls the line_out, center, and lfe output attenuators. reset register (index 00h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 0090h notes all registers not shown and bits containing an x are assumed to be reserved. writing any value to this register performs a register reset, which causes all registers to revert to their default values (exc ept 74h, which forces the serial configuration). reading this register returns the id code of the part and a code for the type of 3d stereo enhancement. id[9:0] identify capability. the id decodes the capabilities of ad1980 based on the following: bit = 1 function ad1980 id0 dedicated mic pcm in channel 0 id1 modem line codec support 0 id2 bass and treble control 0 id3 simulated stereo (mono to stereo) 0 id4 headphone out support 1 id5 loudness (bass boost) support 0 id6 18-bit dac resolution 0 id7 20-bit dac resolution 1 id8 18-bit adc resolution 0 id9 20-bit adc resolution 0 se[4:0] stereo enhancement. the ad1980 does not provide hardware 3d stereo enhancement. (all bits are zeros.) rmv[5:0] right master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. rm right channel mute. once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the mm bit. otherwise this bit will always read ??and will have no effect when set to ?. lmv[5:0] left master volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. mm headphones volume mute. when this bit is set to ?,?both the left and the right channels are muted, unless the msplt bit in register 76h is set to ?.
rev. 0 ad1980 ?1 table i. volume settings for master and headphone control bits reg. 76h master volume (02h) and headphone volume (04h) left channel volume d[13:8] right channel volume d[5:0] msplt * d15 write readback function d7 * write readback function 00 00 0000 00 0000 0 db gain x 00 0000 00 0000 0 db gain 00 00 1111 00 1111 ?2.5 db gain x 00 1111 00 1111 ?2.5 db gain 00 01 1111 01 1111 ?6.5 db gain x 01 1111 01 1111 ?6.5 db gain 00 1x xxxx 01 1111 ?6.5 db gain x 1x xxxx 01 1111 ?6.5 db gain 01 xx xxxx xx xxxx db gain, muted x xx xxxx xx xxxx db gain, muted 10 1x xxxx 01 1111 ?6.5 db gain 1 xx xxxx xx xxxx db gain, only right muted 11 xx xxxx xx xxxx db gain, left only muted 0 xx xxxx xx xxxx ?6.5 db gain 11 xx xxxx xx xxxx db gain, left muted 1 xx xxxx xx xxxx db gain, right muted * for ac ?7 compatibility, bit d7 is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect. x in the above table is ?on? care. mono volume register (index 06h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 * d4 d3 d2 d1 d0 default 06h mono volume mvm x x x x x x x x x mv5 mv4 mv3 mv2 mv1 mv0 8000h * refer to table ii for examples. this register controls the mono output volume and mute bit. the volume register contains five b its, generating 32 volume levels with 31 steps of 1.5 db each. because ac ?7 defines 6-bit volume registers, to maintain compatibility, whenever the d5 bit is set t o ?,?their respective lower five vol- ume bits are automatically set to ??by the codec logic. on readback, all lower five bits will read ?s?whenever this bit is set to ?.?all registers not shown and bits containing an x are assumed to be reserved. mv[5:0] mono volume control. the least significant bit represents 1.5 db. this register controls the output from 0 db to a maximum attenuation of 46.5 db. mvm mono volume mute. when this bit is set to ?,?the channel is muted. table ii. volume settings for mono control bits d[4:0] for mono (06h) d15 write readback function 00 0000 0 0000 0 db gain 00 1111 0 1111 ?2.5 db gain 01 1111 1 1111 ?6.5 db gain 1x xxxx x xxxx db gain, muted x in the above table is a wild card and has no effect on the value. headphones volume register (index 04h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 04h headphones hpm x lhv5 lhv4 lhv3 lhv2 lhv1 lhv0 hprm * x rhv5 rhv4 rhv3 rhv2 rhv1 rhv0 8000h volume * for ac ?7 compatibility, bit d7 is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect.
rev. 0 ?2 ad1980 phone_in volume register (index 0ch) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0ch phone_in volume phm x x x x x x x x x x phv4 phv3 phv2 phv1 phv0 8008h all registers not shown and bits containing an x are assumed to be reserved. refer to table iii for examples. phv[4:0] phone volume. allows setting the phone volume attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the gain range is +12 db to ?4.5 db. the default value is 0 db, with the mute bit enabled. phm phone mute. when this bit is set to ?,?the phone channel is muted. mic volume register (index 0eh) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 0eh mic volume mcm x x x x x x x x m20 x mcv4 mcv3 mcv2 mcv1 mcv0 8008h all registers not shown, and bits containing an x are assumed to be reserved. refer to table iii for examples. mcv[4:0] mic volume gain. allows setting the mic volume attenuator in 32 volume levels. the lsb represents 1.5 db, and the gain range is +12 db to ?4.5 db. the default value is 0 db, with mute enabled. m20 mic gain boost. this bit allows setting additional mic gain to increase the microphone sensitivity. the nominal gain boost by default is 20 db, however, bits d0 and d1 (mbg[1:0]) on the miscellaneous control bits register (76h) allow changing the gain boost to 10 db or 30 db, if necessary. 0 = disabled; gain = 0 db 1 = enabled; default gain = 20 db (see register 76h, bits d0, d1) mcm mic mute. when this bit is set to ?,?the channel is muted. table iii. volume settings for phone and mic control bits d[4:0] phone (0ch) and mic (0eh) d15 write readback function 00 0000 0 0000 12 db gain 00 1000 0 1000 0 db gain 01 1111 1 1111 ?4.5 db gain 1x xxxx x xxxx db gain, muted x in the above table is a wild card, and has no effect on the value.
rev. 0 ad1980 ?3 cd volume register (index 12h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 12h cd volume cvm x x lcv4 lcv3 lcv2 lcv1 lcv0 cdrm * xx rcv4 rcv3 rcv2 rcv1 rcv0 8808h * for ac ?7 compatibility, bit d7 is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, the bit d7 has no effect. all registers not shown and bits containing an x are assumed to be reserved. ref er to table iv for examples. line-in volume register (index 10h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 10h line-in volume lvm x x llv4 llv3 llv2 llv1 llv0 lvrm * xx rlv4 rlv3 rlv2 rlv1 rlv0 8808h * for ac ?7 compatibility, bit d7 is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, the bit d7 has no effect. all registers not shown and bits containing an x are assumed to be reserved. ref er to table iv for examples. rlv[4:0] right line-in volume. allows setting the line-in right channel attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the range is +12 db to ?4.d db. the default value is 0 db, mute enabled. rm right channel mute. once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the lim bit. otherwise, this bit will always read ??and will have no effect when set to ?. llv[4:0] left line-in volume. allows setting the line-in left channel attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. lvm line-in mute. when this bit is set to ?,?both the left and the right channels are muted, unless the msplt bit in register 76h is set to ?,?in which case this mute bit will only affect the left channel. rcv[4:0] right cd volume. allows setting the cd right channel attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. rm right channel mute. once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the cvm bit. otherwise this bit will always read ??and will have no effect when set to ?. lcv[4:0] left cd volume. allows setting the cd left channel attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. cvm cd volume mute. when this bit is set to ?,?both the left and the right channels are muted, unless the msplt bit in register 76h is set to ?,?in which case this mute bit will affect only the left channel. rav[4:0] right aux volume. allows setting the aux right channel attenuator in 32 volume levels with 31 steps of 1.5 db each. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. rm right channel mute. once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the avm bit. otherwise, this bit will always read ??and will have no affect when set to ?. lav[4:0] left pcm out volume. allows setting the pcm left channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. avm pcm out volume mute. when this bit is set to ?,?both the left and the right channels are muted, unless the msplt bit in register 76h is set to ?,?in which case this mute bit will affect only the left channel. aux volume register (index 16h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 16h aux volume avm x x lav4 lav3 lav2 lav1 lav0 avrm * xx rav4 rav3 rav2 rav1 rav0 8808h * for ac ?7 compatibility, bit d7 is only available by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect. all registers not shown and bits containing an x are assumed to be reserved. refer t o table iv for examples.
rev. 0 ?4 ad1980 rov[4:0] right pcm out volume. allows setting the pcm right channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the gain range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. rm right channel mute. once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the avm bit. otherwise, this bit will always read ??and will have no affect when set to ?. lov[4:0] left pcm out volume. allows setting the pcm left channel attenuator in 32 volume levels. the lsb represents 1.5 db, and the range is +12 db to ?4.5 db. the default value is 0 db, mute enabled. om pcm out volume mute. when this bit is set to ?,?both the left and the right channels are muted, unless the msplt bit in register 76h is set to ?,?in which case this mute bit will affect only the left channel. pcm-out volume register (index 18h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 18h pcm out volume om x x lov4 lov3 lov2 lov1 lov0 omrm * xx rov4 rov3 rov2 rov1 rov0 8808h * for ac ?7 compatibility, bit d7 is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect. all registers not shown and bits containing an x are assumed to be reserved. refer t o table iv for examples. note that depending on the state of the ac97nc bit in register 76h, this register has the following additional functionality: for ac87nc = 0, the register also controls the surround, center, and lfe dac gain/attenuators. for ac97nc = 1, the register controls the pcm out volume only. table iv. volume settings for line-in, cd volume, aux, and pcm-out control bits reg. 76h line-in (10h), cd (12h), aux (16h) and pcm-out (18h) left channel volume d[12:8] right channel volume d[4:0] msplt * d15 write readback function d7 * write readback function 00 0 0000 0 0000 12 db gain x 0 0000 0 0000 12 db gain 00 0 1000 0 1000 0 db gain x 0 1000 0 1000 0 db gain 00 1 1111 1 1111 ?4.5 db gain x 1 1111 1 1111 ?4.5 db gain 01 x xxxx x xxxx db gain, muted x x xxxx x xxxx db gain, muted 10 1 1111 1 1111 ?4.5 db gain 1 x xxxx x xxxx db gain, right only muted 11 x xxxx x xxxx db gain, 0 1 1111 1 1111 ?4.5 db gain left only muted 11 x xxxx x xxxx db gain, left muted 1 x xxxx x xxxx db gain, right muted * for ac ?7 compatibility, bit d7 is only available by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, rm bit has no effect. x in the above table is ?on? care. record select control register (index 1ah) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 1ah record select x x x x x ls2 ls1 ls0 x x x x x rs2 rs1 rs0 0000h all registers not shown and bits containing an x are assumed to be reserved. refer to table v for examples. used to select the record source, independently for the right and left channels. for single mic recording, see ms bit (register 20h) for mic1 and mic2 input selection. for dual mic recording, see 2cmic bit (register 76h) to enable simultaneous recording into the left and the right channels. the default value is 0000h, which corresponds to mic input for both channels. rs [2:0] right record select ls [2:0] left record select
rev. 0 ad1980 ?5 table v. settings for record select control ls [10:8] left record source rs [2:0] right record source 000 mic 000 mic 001 cd_l 001 cd_r 010 muted 010 muted 011 aux_l 011 aux_r 100 line_in_l 100 line_in_r 101 stereo mix (l) 101 stereo mix (r) 110 mono mix 110 mono mix 111 phone_in 111 phone_in rim[3:0] right input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db, and the gain range is 0 db to 22.5 db. rm right channel mute. once enabled by the msplt bit in register 76h, this bit mutes the right channel separately from the im bit. otherwise, this bit will always read ??and will have no effect when set to ?. lim[3:0] left input mixer gain control. each lsb represents 1.5 db, 0000 = 0 db, and the gain range is 0 db to 22.5 db. im input mute. when this bit is set to ?,?both the left and the right channels are muted, unless the msplt bit in register 76h is set to ?,?in which case this mute bit will affect only the left channel. table vi. settings for record gain register control bits reg. 76h record gain (1ch) left channel input mixer d[11:8] right channel input mixer d[3:0] msplt * d15 write readback function d7 * write readback function 00 1111 1111 22.5 db gain x 1111 1111 22.5 db gain 00 0000 0000 0 db gain x 0000 0000 0 db gain 01 xxxx xxxx db gain, muted x xxxx xxxx db gain, muted 10 1111 1111 22.5 db gain 1 xxxx xxxx db gain, right only muted 11 xxxx xxxx db gain, 0 1111 1111 22.5 db gain left only muted 11 xxxx xxxx db gain, 1 xxxx xxxx db gain, right muted left muted * for ac ?7 compatibility, bit d7 (rm) is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect. x is ?on? care. record gain register (index 1ch) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 1ch record gain im x x x lim3 lim2 lim1 lim0 imrm * xx x rim3 rim2 rim1 rim0 8000h * for ac ?7 compatibility, bit d7 is available only by setting the msplt bit, register 76h. the msplt bit enables separate mute bits for the left and right channels. if msplt is not set, bit d7 has no effect. all registers not shown, and bits containing an x are assumed to be reserved. refer to table vi for examples.
rev. 0 ?6 ad1980 general-purpose register (index 20h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 20h general-purpose x x x x drss1 drss0 x ms lpbk x x x x x x x 0000h this register should be read before writing to generate a mask for only the bit(s) that need to be changed. all registers not s hown and bits containing an x are assumed to be reserved. lpbk loopback control. this bit enables the digital internal loopback from the adc to the front dac. this feature is normally used for test and troubleshooting. 0 = no loopback (default) 1 = loopback pcm digital data from adc output to dac see lbks bit in register 0x74 for changing the loopback path to use the surround or center/lfe dacs. ms mic select. selects mono mic input. 0 = select mic1 1 = select mic2 see 2cmic bit in register 76h to enable stereo microphone recording. drss [1:0] double rate slot select. the drss bits specify the slots for the n + 1 sample outputs. pcm l (n + 1) and pcm r (n + 1) data are by default provided in output slots 10 and 11. 00: pcm l, r n + 1 data is on slots 10, 11 (reset default) 01: pcm l, r n + 1 data is on slots 7, 8 10: reserved 11: reserved pg[3:0] page selector (read only). this register is used to describe page selector capability for extended features. reading these bits returns 0h, which describes page selection as vendor specific only. i0 interrupt enable (r/w). this enables interrupt generation. 0 = interrupt generation is masked (default) 1 = interrupt generation is unmasked the s/w should not unmask the interrupt unless ensured by the ac ?7 controller that no conflict is possible with modem slot 12 gpi functionality. ac ?7 2.2 compliant controllers will not likely support audio codec interrupt infrastructure. in that case, s/w could poll the interrupt status after initiating a sense cycle and waiting for sense cycle max delay to determine if an inter- rupting event has occurred. i4 interrupt status (r/w). this bit provides interrupt status and clear capability. 0 = interrupt is clear 1 = interrupt was generated interrupt event is cleared by writing a ??to this bit. the interrupt bit will change regardless of condition of inter- rupt enable (i0) status. an interrupt in the gpi in slot 12 in the ac link will follow this bit change when interrupt enable (i0) is unmasked. audio interrupt and paging mechanism register (index 24h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 24h audio interrupt i4 x x x i0 x xxxxxxpg3pg2pg1pg0 xxxxh and paging this register controls the audio interrupt and paging mechanism. all registers not shown and bits containing an x are assumed t o be reserved.
rev. 0 ad1980 ?7 power-down control/status register (index 26h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 26h power-down eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 xxxxrefanldacadcna control/status the ready bits are read only; writing to ref, anl, dac, adc will have no effect. these bits indicate the status for the ad1980 subsections. if the bit is a 1, then that subsection is ready . ready is defined as the subsection able to perform in its nominal state. all registers not shown and bits containing an x are assume d to be reserved. adc adc sections ready to transmit data dac dac sections ready to transmit data anl analog amplifiers, attenuators and mixers ready ref voltage references, v ref and v refout up to nominal level pr[6:0] codec power-down modes. the first three bits are to be used individually rather than in combination with each other. pr3 can be used in combination with pr2 or by itself. the mixer and reference cannot be powered down via pr3 unless the adcs and dacs are also powered down. nothing else can be powered up until the reference is up. pr5 has no effect unless all adcs, dacs, and the ac-link are powered down. the reference and the mixer can be either up or down, but all power-up sequences must be allowed to run to completion before pr5 and pr4 are both set. in multiple codec systems, the master codec? pr5 and pr4 bits control the slave codec. pr5 is also effective in the slave codec if the master? pr5 bit is clear, but the pr4 bit has no effect except to enable or disable pr5. eapd external audio power-down control. controls the state of the eapd pin. eapd = 0 sets the eapd pin low, enabling an external power amplifier (reset defaults). eapd = 1 sets the eapd pin high, shutting off the external power amplifier.
rev. 0 ?8 ad1980 normal adcs off pr0 dacs off pr1 analog off pr2 or pr3 digital i/f off pr4 shut off ac-l ink pr0 = 1 pr1 = 1 pr2 = 1 pr4 = 1 default pr0 = 0 and adc = 1 pr1 = 0 and dac = 1 pr2 = 0 and anl = 1 w arm reset cold reset ready = 1 figure 8. one example of ac ?7 power-down/power-up flow extended audio id register (index 28h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 28h ext? audio id1 id0 x x rev1 rev0 amap ldac sdac cdac dsa1 dsa0 x spdif dra vra x3c7h the extended audio id register identifies which extended audio features are supported. a nonzero extended audio id value indica tes one or more of the extended audio features are supported. all registers not shown and bits containing an x are assumed to be reserved. vra variable rate pcm audio support (read only). this bit returns a ??when read to indicate that the variable rate pcm audio is supported. dra double rate audio (read only). this bit returns a ??when read to indicate that the optional double rate rcm audio is supported for pcm l and pcm r. spdif spdif support (read only). this bit returns a ??when read to indicate that the spdif transmitter is supported (iec958). this bit is also used to validate that the spdif transmitter output is actually enabled. the spdif bit is only allowed to be set high if the spdif pin (48) is pulled down at power-up, enabling the codec transmitter logic. if the spdif pin is floating or pulled high at power-up, the transmitter logic is disabled and therefore this bit returns a low, indicating that the spdif transmitter is not available. this bit must always be read back to verify that the spdif transmitter is actually enabled. dsa[1,0] dac slot assignments (read/write) (reset default = 00) 00 dacs 1, 2 = 3 and 4 dacs 3, 4 = 7 and 8 dacs 5, 6 = 6 and 9 01 dacs 1, 2 = 7 and 8 dacs 3, 4 = 6 and 9 dacs 5, 6 = disabled 10 dacs 1, 2 = 6 and 9 dacs 3, 4 = disabled dacs 5, 6 = disabled 11 reserved cdac pcm center dac support (read only). this bit returns a ??when read to indicate that pcm center dac is supported. sdac pcm surround dac support (read only). this bit returns a ??when read to indicate that pcm surround left and right dacs are supported. ldac pcm lfe dac support (read only), this bit returns a ??when read to indicate that pcm lfe dac is supported. amap slot dac mappings based on codec id (read only). this bit returns a ??when read to indicate that slot/dac mappings based on codec id are supported. rev[1,0] rev[1,0] = 01 indicates codec is ac ?7 revision 2.2 compliant (read only). id[1:0] indicates codec configuration (read only). 00 = primary 01, 10, 11 = secondary
rev. 0 ad1980 ?9 extended audio status and control register (index 2ah) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 2ah extended audio vforce x prk prj pri spcv x eldac esdac ecdac spsa1 spsa0 x espdif edra evra 0xx0h stat/ctrl the extended audio status and control register is a read/write register that provides status and control of the extended audio features. all registers not shown and bits containing an x are assumed to be reserved. evra variable rate audio (read/write). vra = 0, sets fixed sample rate audio at 48 khz (reset default). vra = 1, enables variable rate audio mode (enables sample rate registers and slotreq signaling). edra double rate audio. dra = 1 enables double rate audio mode in which data from pcm l and pcm r in output slots 3 and 4 is used in conjunction with pcm l (n + 1) and pcm r (n + 1) data to provide dac streams at twice the sample rate desig- nated by the pcm front sample rate control register. when using the double rate audio only the front dacs are supported, and all other dacs (surround, center, and lfe) are automatically powered down. note that dra can be used without vra; in that case the converter rates are forced to 96 khz if dra = 1. espdif spdif transmitter subsystem enable/disable bit (read/write). spdif = 1 enables the spdif transmitter. spdif = 0 disables the spdif transmitter (default). spsa[1,0] spdif slot assignment bits (read/write). these bits control the spdif slot assignment and respective defaults, depending on the codec id configuration. see the following table. ecdac center dac status (read only). cdac = 1 indicates the pcm center dac is ready. esdac surround dac status (read only). sdac = 1 indicates the pcm surround dacs are ready. eldac lfe dac status (read only). ldac = 1 indicates the pcm lfe dac is ready. spcv spdif configuration valid (read only). indicates the status of the spdif transmitter subsystem, enabling the driver to determine if the currently programmed spdif configuration is supported. spcv is always valid, indepen- dent of the spdif enable bit status. spcv = 0 indicates current spdif configuration (spsa, spsr, dac slot rate, drs) is not valid (not supported). spcv = 1 indicates current spdif configuration (spsa, spsr, dac slot rate, drs) is valid (supported). pri center dac power-down (read/write). prj = 1 turns off the pcm center dac. prj surround dacs power-down (read/write). prj = 1 turns off the pcm surround dacs. prk lfe dac power-down (read/write). prj = 1 turns off the pcm lfe dac. vforce validity force bit (reset default = 0). when asserted, this bit forces the spdif stream validity flag (bit 28 within each spdif l/r subframe) to be con- trolled by the v bit (d15) in register 3ah (spdif control register). vforce = 0 and v = 0; the validity bit is managed by the codec error detection logic. vforce = 0 and v = 1; the validity bit is forced high, indicating subframe data is invalid. vforce = 1 and v = 0; the validity bit is forced low, indicating subframe data is valid. vforce = 1 and v = 1; the validity bit is forced high, indicating subframe data is invalid.
rev. 0 ?0 ad1980 ac ?7 2.2 amap compliant default spdif slot assignments codec id function spsa = 00 spsa = 01 spsa = 10 spsa = 11 00 2-ch primary w/spdif 3 and 4 7 and 8 [default] 6 and 9 10 and 11 00 4-ch primary w/spdif 3 and 4 7 and 8 6 and 9[default] 10 and 11 00 6-ch primary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11[default] 01 +2-ch secondary w/spdif 3 and 4 7 and 8 6 and 9[default] 01 +4-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11[default] 10 +2-ch secondary w/spdif 3 and 4 7 and 8 6 and 9[default] 10 +4-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11[default] 11 +2-ch secondary w/spdif 3 and 4 7 and 8 6 and 9 10 and 11[default] pcm front dac rate register (index 2ch) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 2ch pcm front srf15 srf14 srf13 srf12 srf11 srf10 srf9 srf8 srf7 srf6 srf5 srf4 srf3 srf2 srf1 srf0 bb80h dac rate this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. srf[15:0] sample rate. the sampling frequency range is from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. if zero is written to vra, then the sample rate is reset to 48 khz. pcm lfe (and center) dac rate register (index 30h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 30h pcm lfe/ srcl15 srcl14 srcl13 srcl12 srcl11 srcl10 srcl9 srcl8 srcl7 srcl6 srcl5 srcl4 srcl3 srcl2 srcl1 srcl0 bb80h c dac rate this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. this register sets the sample rate for the lfe dac and center dac. this register? reset default is to be locked to the pcm fro nt dac sample rate register (2-ch) . to unlock the register bit, sru in register 76h must be asserted. srcl[15:0] sample rate. the sampling frequency range is from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. if zero is written to vra, then the sample rate is reset to 48 khz. pcm surround dac rate register (index 2eh) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 2eh pcm surr srs15 srs14 srs13 srs12 srs11 srs10 srs9 srs8 srs7 srs6 srs5 srs4 srs3 srs2 srs1 srs0 bb80h dac rate this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. this register sets the sample rate for the surround dac. this register? reset default is to be locked to the pcm front dac sam ple rate register (2-ch). to unlock this register, bit sru in register 76h must be asserted. srs[15:0] sample rate. the sampling frequency range is from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. if zero is written to vra bit, then the sample rate is reset to 48 khz. pcm adc rate register (index 32h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 32h pcm l/r sra15 sra14 sra13 sra12 sra11 sra10 sra9 sra8 sra7 sra6 sra5 sra4 sra3 sra2 sra1 sra0 bb80h adc rate this read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in hz. sra[15:0] sample rate. the sampling frequency range is from 7 khz (1b58h) to 48 khz (bb80h) in 1 hz increments. if zero is written to vra, then the sample rate is reset to 48 khz.
rev. 0 ad1980 ?1 cnt[5:0] center volume control cm center v olume mute. when this bit is set to ?,?the channel is muted. lfe[5:0] lfe volume control lm lfe volume mute. when this bit is set to ?,?the channel is muted. center/lfe volume control register (index 36h) reg no. name d15 d14 d13 * d12 d11 d10 d9 d8 d7 d6 d5 * d4 d3 d2 d1 d0 default 36h center/lfe lm x lfe5 lfe4 lfe3 lfe2 lfe1 lfe0 cm x cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 8080h volume all registers not shown and bits containing an x are assumed to be reserved. refer to table vii for examples. this register controls the lfe output volume and mute bit. the volume registers contain five b it, generating 32 volume levels with 31 steps of 1.5 db each. if msplt is not set, bit d7 has no effect. * because ac ?7 defines 6-bit volume registers, to maintain compatibility, whenever the d5 or d13 bit is set to ?,?its respect ive lower five volume bits are automati- cally set to ??by the codec logic. on readback, all lower five bits will read ?? whenever this bit is set to ?. note that depending on the state of the ac97nc bit in register 76h, this register operates as follows: for ac97nc = 0, the register controls the center and lfe output pin attenuators. range is 0 db to ?6.5 db. for ac97nc = 1, the register controls the center and lfe dac gain/attenuators. range is +12 db to ?4.5 db. table vii. settings for center/lfe register control bits center and lfe volume (36h) center d[5:0] and lfe d[13:8] d15/d7 write readback function with ac97nc = 0 function with ac97nc = 1 0 00 0000 00 0000 0 db gain 12 db gain 0 00 1111 00 1111 ?2 db gain ?0.5 db gain 0 01 1111 01 1111 ?6.5 db gain ?4.5 db gain 0 1x xxxx 01 1111 ?6.5 db gain not applicable 1 xx xxxx xx xxxx muted muted surround volume control register (index 38h) reg no. name d15 d14 d13 * d12 d11 d10 d9 d8 d7 d6 d5 * d4 d3 d2 d1 d0 default 38h surround mute_l x lsr5 lsr4 lsr3 lsr2 lsr1 lsr0 mute_r x rsr5 rsr4 rsr3 rsr2 rsr1 rsr0 8080h volume * refer to table viii for examples. this register controls the surround volume controls for both stereo channels and mute bits. e ach volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 db each. because ac ?7 defines 6-bit volume registers, to maintain compatibility, whenever the d5 or d13 bit is set to 1, its respective lower five volume bits are automatically set to ??by the coded logic. on readback , all lo wer five bits will read 1s?whenever these bits are set to 1. note that depending on the state of the ac97nc bit in register 0x76, this register operates as follows: for ac97nc = 0, the register controls the surround output pin attenuators. range is 0 db to ?6.5 db. for ac97nc = 1, the register controls the surround dac gain/attenuators. range is +12 db to ?4.5 db. rsr[5:0] right surround volume control mute_r right surround volume mute. when this bit is set to ?,?the right channel is muted. lsr[5:0] left surround volume control mute_l left surround volume mute. when this bit is set to ?,?the left channel is muted.
rev. 0 ?2 ad1980 spdif control register (index 3ah) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 3ah spdif v x spsr1 spsr0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy /aud pro 2000h control all registers not shown and bits containing an x are assumed to be reserved. register 3ah is a read/write register that controls spdif functionality and manages bit fields propagated as channel status (or subframe in the v case). with the exception of v, this register should only be written to when the spdif transmitter is disabled (spdif bit in register 2ah is ? ?. this ensures that control and status information starts up correctly at the beginning of spdif transmission. pro professional. ??indicates professional use of channel status, ??indicates consumer. /aud non-audio. ??indicates data is non pcm format, ??indicates data is pcm. copy copyright. ??indicates copyright is asserted, ??indicates copyright is not asserted. pre pre-emphasis. ??indicates filter pre-emphasis is 50 s/15 s, ??indicates pre-emphasis is none. cc[6-0] category code. programmed according to iec standards, or as appropriate. lg eneration level. programmed according to iec standards, or as appropriate. spsr[1,0] spdif transmit sample rate: spsr[1:0] = ?0?transmit sample rate = 44.1 khz spsr[1:0] = ?1?reserved spsr[1:0] = ?0?transmit sample rate = 48 khz (default) spsr[1:0] = ?1?not supported. vv alidity. this bit affects the validity flag (bit 28 transmitted in each spdif l/r subframe) and enables the spdif transmitter to maintain connection during error or mute conditions. v = 1 each spdif subframe (l+r) has bit 28 set to ?.?this tags both samples as invalid. v = 0 each spdif subframe (l+r) has bit 28 set to ??for valid data and ??for invalid data (error condition). note that when v = 0, asserting the vforce bit (d15) in register 2ah (ext? audio stat/ctrl) will force the va- lidity flag low, marking both samples as valid. table viii. settings for surround register control bits surround volume (38h) left surround d[13:8] right surround d[5:0] d15/d7 write readback function with ac97nc = 0 function with ac97nc = 1 0 00 0000 00 0000 0 db gain 12 db gain 0 00 1111 00 1111 ?2 db gain ?0.5 db gain 0 01 1111 01 1111 ?6.5 db gain ?4.5 db gain 0 1x xxxx 01 1111 ?6.5 db gain not applicable 1 xx xxxx xx xxxx muted muted
rev. 0 ad1980 ?3 bca[5,0] biquad and coefficient address pointer: biquad 0 coef a0 bca[5,0] = 011011 biquad 0 coef a1 bca[5,0] = 011010 biquad 0 coef a2 bca[5,0] = 011001 biquad 0 coef b1 bca[5,0] = 011101 biquad 0 coef b2 bca[5,0] = 011100 biquad 1 coef a0 bca[5,0] = 100000 biquad 1 coef a1 bca[5,0] = 011111 biquad 1 coef a2 bca[5,0] = 011110 biquad 1 coef b1 bca[5,0] = 100010 biquad 1 coef b2 bca[5,0] = 100001 biquad 2 coef a0 bca[5,0] = 100101 biquad 2 coef a1 bca[5,0] = 100100 biquad 2 coef a2 bca[5,0] = 100011 biquad 2 coef b1 bca[5,0] = 100111 biquad 2 coef b2 bca[5,0] = 100110 biquad 3 coef a0 bca[5,0] = 101010 biquad 3 coef a1 bca[5,0] = 101001 biquad 3 coef a2 bca[5,0] = 101000 biquad 3 coef b1 bca[5,0] = 101100 biquad 3 coef b2 bca[5,0] = 101011 biquad 4 coef a0 bca[5,0] = 101111 biquad 4 coef a1 bca[5,0] = 101110 biquad 4 coef a2 bca[5,0] = 101101 biquad 4 coef b1 bca[5,0] = 110001 biquad 4 coef b2 bca[5,0] = 110000 biquad 5 coef a0 bca[5,0] = 110100 biquad 5 coef a1 bca[5,0] = 110011 biquad 5 coef a2 bca[5,0] = 110010 biquad 5 coef b1 bca[5,0] = 110110 biquad 5 coef b2 bca[5,0] = 110101 biquad 6 coef a0 bca[5,0] = 111001 biquad 6 coef a1 bca[5,0] = 111000 biquad 6 coef a2 bca[5,0] = 110111 biquad 6 coef b1 bca[5,0] = 111011 biquad 6 coef b2 bca[5,0] = 111010 chs channel select. chs = 0 selects left channel coefficients data block. chs = 1 selects right channel coefficients data block. sym symmetry. when set to ?,?this bit indicates that the left and right channel coefficients are equal. this shortens the coeffi- cients?setup sequence since only the left channel coefficients need to be addressed and set up. (the right channel coefficients are fetched from the left channel memory.) eqm equalizer mute. when set to ?,?this bit disables the equalizer function (allows all data pass through). the reset default sets this bit to ?,?disabling the equalizer function until the biquad coefficients can be properly set. eq control register (index 60h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 60h eq ctrl eqm x x x x x x x sym chs bca5 bca4 bca3 bca2 bca1 bca0 8080h all registers not shown, and bits containing an x are assumed to be reserved. register 60h is a read/write register that controls the equalizer functionality and data setup. this register also contains the biquad and coefficient address pointer, which is used in conjunction with the eq data register (78h) to set up the equalizer coefficients. the reset default disables t he equalizer function until the coeffi- cients can be properly set up by the software and sets the symmetry bit to allow equal coefficients for the left and right chan nels.
rev. 0 ?4 ad1980 js0int indicates pin js0 has generated an interrupt. remains set until the software services js0 interrupt, i.e., js0 isr should clear this bit by writing a ??to it. note that the interrupt to the system is actually an or combination of this bit and js1int. also, note that the actual interrupt implementation is selected by the ints bit (register 76h). it is also possible to generate a software system interrupt by writing a ??to this bit. js1int indicates pin js1 has generated an interrupt. remains set until the software services js1 interrupt, i.e., js1 isr should clear this bit by writing a ??to it. see the js0int description for additional details. js0st js0 state. this bit always reports the logic state of js0 pin. js1st js1 state. this bit always reports the logic state of js1 pin. js0md js0 mode. this bit selects the operation mode for the js0 pin. 0 = jack sense mode (reset default) 1 = interrupt mode js1md js1 mode. this bit selects the operation mode for the js1 pin. 0 = jack sense mode (reset default) 1 = interrupt mode js0tmr js0 timer enable. if this bit is set to a ?,? js0 must be high for greater than 278 ms to be recognized. js1tmr js1 timer enable. if this bit is set to a ?,? js1 must be high for greater than 278 ms to be recognized. js0eqb js0 eq bypass enable. this bit enables js0 to control the eq bypass. when this bit is set to ?,? js0 = 1 will cause the eq to be bypassed. js1eqb js1 eq bypass enable. this bit enables js1 to control the eq bypass. when this bit is set to ?,? js1 = 1 will cause the eq to be bypassed. jsmt[2,0] js mute enable selector. these three bits select and enable the jack sense muting action (see table ix). js0dmx js0 down = mix control enable. this bit enables js0 to control the down-mix function. this function allows a digital mix of six channels of audio into 2-channel audio. the mix can then be routed to the stereo line_out or hp_out jacks. when this bit is set to ?,?js0 = 1 will activate the down-mix conversion. see the dmix description in register 76h. the dmix bits select the down-mix implementation type and can also force the function to be activated. js1dmx js1 down mix control enable. this bit enables 2-channel to 6-channel audio spread function when both jack senses are active (logic state ??. note that the sprd bit can also force the spread function without being gated by the jack senses. see this bit? description in register 76h for a better understanding of the spread function. jssprd js spread control enable. this bit enables 2-channel to 6-channel audio spread function when both jack senses are active (logic state ??. note that the sprd bit can also force the spread function without being gated by the jack senses. see this bit? description in register 76h for a better understanding of the spread function. jack sense/audio interrupt status register (index 72h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 72h jack js1 js1 js0 js js js js1 js0 js1 js0 js1 js0 js1 js0 js1 js0 0000h sense sprd dmx dmx mt2 mt1 mt0 eqb eqb tmr tmr md md st st int int all register bits are read/write except for js0st and js1st, which are read only. eq data register (index 62h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 62h eq data cfd15 cfd14 cfd13 cfd12 cfd11 cfd10 cfd9 cfd8 cfd7 cfd6 cfd5 cfd4 cfd3 cfd2 cfd1 cfd0 0000h this read/write register is used to transfer eq biquad coefficients into memory. the register data is transferred to, or retrie ved from, the address pointed to by the bca bits in the eq cntrl register (60h). data will only be written to memory if the eqm bit (register 60h, bit 15) is asserted. cfd[15,0] coefficient data. the biquad coefficients are fixed-point format values with 16 bits of resolution. the cfd15 bit is the msb and the cfd0 bit is the lsb.
rev. 0 ad1980 ?5 table ix. jack sense mute select (jsmt [2:0]) hp line c/lfe mono ref js1 js0 jsmt2 jsmt1 jsmt0 out out out out notes 0 out (0) out (0) 0 0 0 active active active active js0 and js1 ignored 1 out (0) in (1) 0 0 0 active active active active 2i n (1) out (0) 0 0 0 active active active active 3i n (1) in (1) 0 0 0 active active active active 4 out (0) out (0) 0 0 1 active fmute fmute active js0 no mute action, 5 out (0) in (1) 0 0 1 active fmute fmute active js1 mutes mono and 6i n (1) out (0) 0 0 1 active active active active enables line_out 7i n (1) in (1) 0 0 1 active active active active and c/lfe. standard 6-channel config swapped hp_out and line_out. 8 out (0) out (0) 0 1 0 fmute active fmute active js0 no mute action, 9 out (0) in (1) 0 1 0 fmute active fmute active js1 mutes mono and 10 in (1) out (0) 0 1 0 active active active fmute enables hp_out 11 in (1) in (1) 0 1 0 active active active fmute and c/lfe. standard 6-channel config no swap. 12 out (0) out (0) 0 1 1 ** ** ** ** ** reserved 13 out (0) in (1) 0 1 1 ** ** ** ** 14 in (1) out (0) 0 1 1 ** ** ** ** 15 in (1) in (1) 0 1 1 ** ** ** ** 16 out (0) out (0) 1 0 0 active fmute fmute active js0 = 0 and js1 = 0 17 out (0) in (1) 1 0 0 active active active fmute enables mono. 18 in (1) out (0) 1 0 0 active fmute fmute fmute js1 = 1 enables front 19 in (1) in (1) 1 0 0 active fmute fmute fmute only. js0 = 1 enables all rear. 6-chan config with front jack wrap back. 20 out (0) out (0) 1 0 1 fmute fmute fmute active js0 no mute action, 21 out (0) in (1) 1 0 1 fmute fmute fmute fmute js1 mutes mono and 22 in (1) out (0) 1 0 1 active active active fmute enables line_out 23 in (1) in (1) 1 0 1 active active active fmute + hp_out + c/ lfe. standard 6-channel config swapped hp_out and line_out. 24 out (0) out (0) 1 1 0 ** ** ** ** reserved 25 out (0) in (1) 1 1 0 ** ** ** 26 in (1) out (0) 1 1 0 ** ** ** 27 in (1) in (1) 1 1 0 ** ** ** 28 out (0) out (0) 1 1 1 ** ** ** ** reserved 29 out (0) in (1) 1 1 1 ** ** ** 30 in (1) out (0) 1 1 1 ** ** ** 31 in (1) in (1) 1 1 1 ** ** ** fmute = output is forced to mute independent of the respective volume register setting. active = output is not muted and its status is dependent on the respective volume register setting. out = nothing plugged into the jack and therefore the js status is ??(via the load resistor pull-down). in = jack has plug inserted and therefore the js status is ??(via the codec js internal pull-up).
rev. 0 ?6 ad1980 serial configuration register (index 74h) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 74h serial slot16 regm2 regm1 regm0 regm3 drf x chen x lbks1 lbks0 ints x spal spdz splnk 1001h configuration all registers not shown and bits containing an x are assumed to be reserved. note that this register is not reset when the reset register (0x00) is written to (soft reset). splnk spdif link. this bit enables the spdif to link with the front dacs for data requesting. 0 = spdif and dac are not linked. 1 = spdif and dac are linked and receive the same data requests (reset default). spdz spdif dacz. 0 = repeat last sample out of the spdif stream if fifo under-runs (reset default). 1 = forces midscale sample out the spdif stream if fifo under-runs. spal spdif adc loop-around. 0 = spdif transmitter is connected to the ac-link stream (reset default). 1= spdif transmitter is connected to the digital adc stream, not the ac-link. ints interrupt mode select. this bit selects the js interrupt implementation path. 0 = bit 0 slot 12 (modem interrupt) (reset default). 1 = slot 6 valid bit (mic adc interrupt). lbks[1:0] loop-back selection. these bits select the internal digital loop-back path when lpbk bit is active (see register 20h) 00 = loop back through the front dacs (reset default). 01 = loop back through the surround dacs. 10 = reserved 11 = loop-back through the center and lfe dacs (center dac loops back from the adc left channel, the lfe dac from the adc right channel). chen chain enable. this bit enables chaining of a slave codec sdata_in stream into the id0 pin (pin 45). 0 = disable chaining (reset default). 1 = enable chaining into id0 pin. drf dac request force. this allows the ad1980 to synchronize dac requests with the ad1981a/b. 0 = normal dac requesting sequence (reset default). 1 = synchronize to ad1981a/b dac requests. regm3 slave 3 codec register mask regm0 master codec register mask regm1 slave 1 codec register mask regm2 slave 2 codec register mask slot16 enable 16-bit slot mode. slot16 makes all ac-link slots 16 bits in length, formatted into 16 slots. this is a preferred mode for dsp serial port interfacing.
rev. 0 ad1980 ?7 mbg[1:0] mic boost gain select register. these two bits allow changing the mic preamp gain from the nominal 20 db gain. both mic1/mic2 and mic2 preamps will be set to the same selected gain. note that this gain takes effect only while bit d6 (m20) on the mic volume register (0eh) is set to 1; otherwise the mic boost block has a gain of 0 db. 00 = 20 db gain (reset default) 01 = 10 db gain 10 = 30 db gain 11 = reserved vrefd v refout disable. disables v refout , placing it into high z out mode. note that this bit overrides the vrefh bit selection (see below). 0 = v refout pin is driven by the internal reference (reset default). 1 = v refout pin is placed into high z out mode. vrefh v refout high. changes v refout from 2.25 v to 3.70 v for pc2001 compliant mic bias applications. 0 = v refout pin is set to 2.25 v output (reset default). 1 = v refout pin is set to 3.70 v output. sru sample rate unlock. controls dac sample rate locking. 0 = all dac sample rates are locked to the front sample rate (reset default). 1 = dac sample rates can be set independently for front, surround, and lfe. losel line_out amplifiers input select. this bit allows the line_out output amplifiers to be driven by the mixer or the surround dacs. the main purpose for this is to allow swapping of the front and surround channels to make better use of the surr/hp_out output amplifiers. this bit should normally be used in tandem with the hpsel bit (see below). 0 = line_out amplifiers are driven by the mixer outputs (reset default). 1 = line_out amplifiers are driven by the surround dac outputs. 2cmic 2-channel mic select. this bit enables simultaneous recording from mic1 and mic2 inputs, using a stereo microphone array. note that this register works in conjunction with the ms bit in register 20h. 0 = mic1 or mic2 (determined by ms bit) is routed to the record selector? left and right mic channels as well as to the mixer (reset default). 1 = mic1 is routed to the record selector? left mic channel and mic2 is routed to the record selector? right mic channel. note that in this mode, the ms bit should be set low and mic1 can still be enabled into the mixer. sprd spread enable. this bit enables spreading of 2-channel media to all six output channels. this function is imple- mented in the analog section by using the output selector controls line for the center/lfe, surround, and line_out output channels. note that the jack sense pins can also be set up to control (gate) this function, depending on the jssprd bit (see register 72h). 0 = no spreading occurs unless activated by the jack senses and jssprd bits (reset default). 1 = the sprd selector drives the center and lfe outputs from the mono_out, the hpsel selector drives the surr/hp_out outputs from the mixer outputs, and the losel selector drives the line_out outputs also from the mixer outputs. note that the sprd bit overrides the current output selector control lines set up by bits losel and hpsel as follows: losel = 0 and hpsel = 1. miscellaneous control bit register (index 76h) reg de- no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 fault 76th misc dacz ac97nc msplt lodis cldis hpsel dmix1 dmix0 sprd 2cmic losel sru vrefh vrefd mbg1mbg0 0000h control bits
rev. 0 ?8 ad1980 dmix[1:0] down mix mode select. provides analog down-mixing of the center, lfe, and/or surround channels into the mixer channels. this allows the full content of 5.1 or quad media to be played through stereo headphones or speakers. note that the jack sense pins can also be set up to control (gate) this function depending on the js0dmx and js1dmx bits (see register 72h). the upper bit allows forcing the down-mix function: dmix[1] = 0, no down-mix unless activated by the jack sense and jsxdmx bits (default). dmix[1] = 1, forces down-mix function. the lower bit selects the down-mix type: dmix[0] = 0, selects 6-to-4 down-mix. the center and lfe channels are summed equally into the mixer left and right channels (default). dmix[0] = 1, selects 6-to-2 down-mix. the surround left and right channels are summed into the mixer left and right channels. default for dmix[1:0] is ?0. hpsel headphone amplifier input select. this bit allows the headphone power amps to be driven from the surround dacs or from the mixer outputs. there are two reasons for this: one is to allow 2-channel media to use the higher power headphone amplifiers available on the surr/hp_out outputs; the other is to allow spreading of 2-channel media to the surround outputs. together with the losel bit (see above), this bit also provides for analog swapping of the mixer (front) and sur- round outputs. 0 = surr_out/hp_out outputs are driven by the surround dacs (reset default). 1 = surr_out/hp_out outputs are driven by the mixer outputs. cldis center and lfe disable. disables the center and lfe output pins, placing them into high-z mode so that the assigned output audio jack(s) can be shared for mic inputs or other functions. 0 = center and lfe output pins have normal audio drive capability (reset default). 1 = center and lfe output pins are placed into high-z mode. lodis line_out disable. disables the line_out pins (l/r), placing them into high-z mode so that the assigned output audio jack can be shared for line input function. 0 = line_out pins have normal audio drive capability (reset default). 1 = line_out pins are placed into high-z mode. msplt mute split. allows separate mute control bits for master, hp, line_in, cd, pcm out, and record volume/gain control registers. 0 = both left and right channel mutes are controlled by bit d15 in the respective registers (reset default). 1 = bit d15 affects only the left channel mute and bit d7 affects only the right channel mute. ac97nc ac ?7 no compatibility mode. this bit allows the surround, center, and lfe volume control registers and output attenuators to operate in a more functional mode than defined by the ac97 2.2 spec. this is called adi compatibility mode. in ac ?7 compatibility mode, the dac gain/attenuators for the surround, center, and lfe are controlled by register 18h (pcm volume). the output pin attenuators for the surround are controlled by register 38h, and the output pin attenuators for the center and lfe are controlled by register 36h. in adi compatibility mode, the surround dac gain/attenuators are controlled by register 38h, and the center/ lfe dac are controlled by register 36h. the output pin attenuators for center/lfe are controlled by register 02h (master volume), and the output pin attenuators for surround are controlled by register 04h. 0 = ac97 compatibility mode (reset default). 1 = adi compatibility mode. dacz dac zero-fill. determines dac data fill under starved condition. 0 = dac data is repeated when dacs are starved for data (reset default). 1 = dac data is zero-filled when dacs are starved for data.
rev. 0 ad1980 ?9 vendor id register (index 7ch?eh) reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 7ch vendor id1 f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 4144h s[7:0] this register is ascii encoded to a. f[7:0] this register is ascii encoded to d. reg no. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 7eh vendor id2 t7 t6 t5 t4 t3 t2 t1 t0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 5370h t[7:0] this register is ascii encoded to s. rev[7:0] this register is set to 70h identifying the ad1980. codec id and clock selection table xtl_in id1# ido# codec id codec clocking source gnd 0 0 secondary, id = 3 12.288 mhz (bit_clk from primary codec) gnd 0 1 secondary, id = 2 12.288 mhz (bit_clk from primary codec) gnd 1 0 secondary, id = 1 12.288 mhz (bit_clk from primary codec) xtal 1 1 primary, id = 0 24.576 mhz local xtal or external clk into xtl_in clk input 0 0 primary, id = 0 14.3181 mhz (external into xtl_in) clk input 0 1 primary, id = 0 48.00 mhz (external into xtl_in) clk input 1 x reserved reserved note that internally, the id pins have weak pull-ups and are inverted.
rev. 0 ?0 ad1980 outline dimensions 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane
?1
c03231??1/02(0) printed in u.s.a. ?2

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